In recent years, with miniaturization and sophistication of electronic devices, a number of technologies designed to increase packaging density of semiconductor devices have been developed. Such technologies include chip-on-chip semiconductor device technologies and package-on-package semiconductor device technologies.
FIG. 1 is a cross-sectional view of a conventional chip-on-chip semiconductor device. On an upper surface of an interposer 84, a semiconductor chip 80 having an upper surface on which a circuit is formed is stacked via an adhesive 82. An external electrode (not shown) provided on the upper surface of the semiconductor chip 80 and a connector terminal (not shown) on the interposer 84 are electrically coupled by a wire 86. On a lower surface of the interposer 84, a solder ball 88 for electrically coupling to the outside is provided. On the upper surface of the interposer 84, a resin section 89 to mold the semiconductor chip 80 and the wire 86 is provided. With this configuration, the packaging density of the semiconductor device can be increased as a plurality of semiconductor chips 80 can be provided in a single package.
FIG. 2 is a cross-sectional view of a package-on-package semiconductor device of a second conventional approach. Components of FIG. 2 common to FIG. 1 have been given the same numbers and their explanations are omitted. A first semiconductor package 90 and a second semiconductor package 92 respectively include semiconductor chip 80, adhesive 82, interposers 84a and 84b, wire 86 and resin section 89. A first solder ball 94 provided on a lower surface of the interposer 84a of the first semiconductor package 90 is bonded to an upper surface of the interposer 84b of the second semiconductor package 92. On a lower surface of the interposer 84b of the second semiconductor package 92, a second solder ball 96 for electrically coupling to the outside is provided. With this configuration (since a plurality of semiconductor packages can be vertically stacked) the packaging density of the semiconductor device can be increased.
Other conventional semiconductor device packaging techniques are commonly used in industry. For example, WO99/56313 (FIG. 20) illustrates a semiconductor device in which a plurality of semiconductor packages are stacked by providing a through electrode on a lead frame where a solder ball is provided on a tip of the through electrode. Published Japanese Translation of PCT Application No. JP-T-2000-510993 discloses a semiconductor device in which electronic components and wirings are electrically bonded by using connector pins. Japanese Patent Application Publication No. JP-A-2003-151714 discloses a method for mounting electronic components to a wiring circuit body using crimp pieces.